CCTV9英语新闻:PBOC reveals new monetary policy tool_CCTV9英语新闻_VOA英语网China's Central Bank has revealed its latest monetary policy tool. It’s known as the Standing Lending Facility, or SLF. The People’s Bank of China launched the SLF already at the beginning of this year, but only now made the information public. The facility aims at providing large amounts of funding to banks when they face a liquidity squeeze, and are unable to get sufficient financing from the interbank market. The SLF has a tenor of one to three months. It functions similar to the US Federal Reserve’s discount window facility. The PBOC says the SLF played an important role in easing China’s liquidity squeeze among its banks in June, which caused the overnight interbank rate to surge by 3. The total value of outstanding SLFs have decreased 5- percent from June to September. The PBOC says this partly shows that liquidity has increased in the Chinese banking system.来自:VOA英语网 文章地址: http: //www. PBOC- reveals- new- monetary- policy- tool.
Central Banking Lessons from the. Ineffective macroprudential tools increase the burden on monetary policy. of Japan’s Monetary Policy and Bank Risk. . monetary policy tool. Bank of Uganda implements monetary policy control through a mix of monetary policy instruments. Uganda's current inflation rate.
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Table of Contents 1.1 STRUCTURED COMPUTER ORGANIZATION 2 1.1.1 Languages, Levels, and Virtual Machines 2 1.1.2 Contemporary Multilevel Machines 5 1.1.3 Evolution of Multilevel Machines 8 1.2 MILESTONES IN COMPUTER ARCHITECTURE. Andrew Stuart 'Andy' Tanenbaum (sometimes referred to by the handle ast) [6] (born March 16, 1944) is an American computer scientist and professor emeritus of computer science at the Vrije Universiteit, Amsterdam in the. PERSONAL INFORMATION. Personal FAQ; Curriculum vitae; BOOKS. Photos of the covers of my books; Translations of my books; Structured Computer Organizaton, 6th ed. Computer Networks, 5th ed. Operating Systems Design and. Is Your Cat Infected with a Computer Virus? Melanie R. Rieback Bruno Crispo Andrew S. Tanenbaum Vrije Universiteit Amsterdam Computer Systems Group De Boelelaan 1081a, 1081 HV Amsterdam, Netherlands fmelanie,crispo,[email protected]. We’re excited to let you know that Computer Networks 5/E (CN5E) now comes with supplemental video lectures! The videos provide enough content for a full quarter or semester course on networking; they have been used as the. Pearson - Structured Computer Organization, 6/EAbout This Product. Structured Computer Organization, specifically written for undergraduate students, is a best- selling guide that provides an accessible introduction to computer hardware and architecture. This text will also serve as a useful resource for all computer professionals and engineers who need an overview or introduction to computer architecture. This book takes a modern structured, layered approach to understanding computer systems. It's highly accessible - and it's been thoroughly updated to reflect today's most critical new technologies and the latest developments in computer organization and architecture. Tanenbaum’s renowned writing style and painstaking research make this one of the most accessible and accurate books available, maintaining the author’s popular method of presenting a computer as a series of layers, each one built upon the ones below it, and understandable as a separate entity. Features. Comprehensive coverage of computer hardware and architecture basics — Uses a clear, approachable writing style to introduce students to multilevel machines, CPU organization, gates and Boolean algebra, microarchitecture, ISA level, flow of controls, virtual memory, and assembly language. Accessible to all students — Covers common devices in a practical manner rather than with an abstract discussion of theory and concepts. Designed for undergraduate students — Not simply a watered- down adaptation of a graduate- level text. New To This Edition. Computer Network Pdf By Andrew Tanenbaum RockridgeComputer Network Pdf By Andrew Tanenbaum OaklandNew co- author, Todd Austin. Updated terminology, trends, and new technologies. Chapter 3: Major update to CPU chip examples to reflect newer, more popular architectures. Chapter 4: New example ISA implemented; discussion on ARM, x. AVR microcontroller ISAs added throughout book. Other bestselling titles by Andrew S. Tanenbaum Structured Computer Organization, 5th edition This widely read classic, now in its fifth edition, provides the ideal introduction to computer architecture. It covers the topic in. About the Author(s) Andrew S. Tanenbaum has an S.B. degree from M.I.T. and a Ph.D. from the University of California at Berkeley. He is currently a Professor of Computer Science at the Vrije Universiteit in Amsterdam, The. Chapter 6: New subsection on I/O “Virtualization”; updated discussion on Support for Parallel Processing. Chapter 8: New section “Parallel Programming Models”New Appendix C: The ARM Architecture (which is the dominant architecture used in mobile and embedded electronics market.)Table of Contents. STRUCTURED COMPUTER ORGANIZATION 2. Languages, Levels, and Virtual Machines 2. Contemporary Multilevel Machines 5. Evolution of Multilevel Machines 8. MILESTONES IN COMPUTER ARCHITECTURE 1. The Zeroth Generation–Mechanical Computers (1. The First Generation–Vacuum Tubes (1. The Second Generation–Transistors (1. The Third Generation–Integrated Circuits (1. The Fourth Generation–Very Large Scale Integration (1. The Fifth Generation–Low- Power and Invisible Computers 2. THE COMPUTER ZOO 2. Technological and Economic Forces 2. The Computer Spectrum 3. Disposable Computers 3. Microcontrollers 3. Mobile and Game Computers 3. Personal Computers 3. Servers 3. 61. 3. Mainframes 3. 81. EXAMPLE COMPUTER FAMILIES 3. Introduction to the x. Architecture 3. 91. Introduction to the ARM Architecture 4. Introduction to the AVR Architecture 4. METRIC UNITS 4. 91. OUTLINE OF THIS BOOK 5. PROCESSORS 5. 52. CPU Organization 5. Instruction Execution 5. RISC versus CISC 6. Design Principles for Modern Computers 6. Instruction- Level Parallelism 6. Processor- Level Parallelism 6. PRIMARYMEMORY 7. 32. Bits 7. 42. 2. 2 Memory Addresses 7. Byte Ordering 7. 62. Error- Correcting Codes 7. Cache Memory 8. 22. Memory Packaging and Types 8. SECONDARYMEMORY 8. Memory Hierarchies 8. Magnetic Disks 8. IDE Disks 9. 12. 3. SCSI Disks 9. 22. RAID 9. 42. 3. 6 Solid- State Disks 9. CD- ROMs 9. 92. 3. CD- Recordables 1. CD- Rewritables 1. DVD 1. 06. 2. 3. 1. Blu- ray 1. 08. 2. INPUT/OUTPUT 1. 08. Buses 1. 08. 2. 4. Terminals 1. 13. 2. Mice 1. 18. 2. 4. Game Controllers 1. Printers 1. 22. 2. Telecommunications Equipment 1. Digital Cameras 1. Character Codes 1. SUMMARY 1. 42. 3. GATES AND BOOLEAN ALGEBRA 1. Gates 1. 48. 3. 1. Boolean Algebra 1. Implementation of Boolean Functions 1. Circuit Equivalence 1. BASIC DIGITAL LOGIC CIRCUITS 1. Integrated Circuits 1. Combinational Circuits 1. Arithmetic Circuits 1. Clocks 1. 68. 3. 3 MEMORY 1. Latches 1. 69. 3. Flip- Flops 1. 72. Registers 1. 74. 3. Memory Organization 1. Memory Chips 1. 78. RAMs and ROMs 1. 80. CPU CHIPS AND BUSES 1. CPU Chips 1. 85. 3. Computer Buses 1. Bus Width 1. 90. 3. Bus Clocking 1. 91. Bus Arbitration 1. Bus Operations 1. EXAMPLE CPU CHIPS 2. The Intel Core i. The Texas Instruments OMAP4. System- on- a- Chip 2. The Atmel ATmega. Microcontroller 2. EXAMPLE BUSES 2. 14. The PCI Bus 2. 15. PCI Express 2. 23. The Universal Serial Bus 2. INTERFACING 2. 32. I/O Interfaces 2. Address Decoding 2. SUMMARY 2. 35. 4. AN EXAMPLE MICROARCHITECTURE 2. The Data Path 2. 44. Microinstructions 2. Microinstruction Control: The Mic- 1 2. AN EXAMPLE ISA: IJVM 2. Stacks 2. 58. 4. 2. The IJVM Memory Model 2. The IJVM Instruction Set 2. Compiling Java to IJVM 2. AN EXAMPLE IMPLEMENTATION 2. Microinstructions and Notation 2. Implementation of IJVM Using the Mic- 1 2. DESIGN OF THE MICROARCHITECTURE LEVEL 2. Speed versus Cost 2. Reducing the Execution Path Length 2. A Design with Prefetching: The Mic- 2 2. A Pipelined Design: The Mic- 3 2. A Seven- Stage Pipeline: The Mic- 4 3. IMPROVING PERFORMANCE 3. Cache Memory 3. 06. Branch Prediction 3. Out- of- Order Execution and Register Renaming 3. Speculative Execution 3. EXAMPLES OF THE MICROARCHITECTURE LEVEL 3. The Microarchitecture of the Core i. CPU 3. 25. 4. 6. 2 The Microarchitecture of the OMAP4. CPU 3. 31. 4. 6. 3 The Microarchitecture of the ATmega. Microcontroller 3. COMPARISON OF THE I7, OMAP4. AND ATMEGA1. 68 3. SUMMARY 3. 39. 5. OVERVIEW OF THE ISA LEVEL5. Properties of the ISA Level. Memory Models. 5. Registers. 5. 1. 4 Instructions. Overview of the Core i. ISA Level. 5. 1. 6 Overview of the OMAP4. ARM ISA Level. 5. Overview of the ATmega. AVR ISA Level. 5. DATA TYPES5. 2. 1 Numeric Data Types. Nonnumeric Data Types. Data Types on the Core i. Data Types on the OMAP4. ARM CPU5. 2. 5 Data Types on the ATmega. AVR CPU5. 3 INSTRUCTION FORMATS5. Design Criteria for Instruction Formats. Expanding Opcodes. The Core i. 7 Instruction Formats. The OMAP4. 43. 0 ARM CPU Instruction Formats. The ATmega. 16. 8 AVR Instruction Formats. ADDRESSING5. 4. 1 Addressing Modes. Immediate Addressing. Direct Addressing. Register Addressing. Register Indirect Addressing. Indexed Addressing. Based- Indexed Addressing. Stack Addressing. Addressing Modes for Branch Instructions. Orthogonality of Opcodes and Addressing Modes. The Core i. 7 Addressing Modes. The OMAP4. 44. 0 ARM CPU Addressing Modes. The ATmega. 16. 8 AVR Addressing Modes. Discussion of Addressing Modes. INSTRUCTION TYPES5. Data Movement Instructions. Dyadic Operations. Monadic Operations. Comparisons and Conditional Branches. Procedure Call Instructions. Loop Control. 5. 5. Input/Output. 5. 5. The Core i. 7 Instructions. The OMAP4. 43. 0 ARM CPU Instructions. The ATmega. 16. 8 AVR Instructions. Comparison of Instruction Sets. FLOWOF CONTROL5. 6. Sequential Flow of Control and Branches. Procedures. 5. 6. Coroutines. 5. 6. Traps. 5. 6. 5 Interrupts. A DETAILED EXAMPLE: THE TOWERS OF HANOI5. The Towers of Hanoi in Core i. Assembly Language. The Towers of Hanoi in OMAP4. ARM Assembly Language. THE IA- 6. 4 ARCHITECTURE AND THE ITANIUM 2. The Problem with the IA- 3. ISA5. 8. 2 The IA- 6. Model: Explicitly Parallel Instruction Computing. Reducing Memory References. Instruction Scheduling. Reducing Conditional Branches: Predication. Speculative Loads. SUMMARY6. 1 VIRTUAL MEMORY6. Paging. 6. 1. 2 Implementation of Paging. Demand Paging and the Working Set Model. Page Replacement Policy. Page Size and Fragmentation. Segmentation. 6. 1. Implementation of Segmentation. Virtual Memory on the Core i. Virtual Memory on the OMAP4. ARM CPU6. 1. 1. 0 Virtual Memory and Caching. VIRTUAL I/O INSTRUCTIONS6. Files. 6. 2. 2 Implementation of Virtual I/O Instructions. Directory Management Instructions. VIRTUAL INSTRUCTIONS FOR PARALLEL PROCESSING6. Process Creation. Race Conditions. 6. Process Synchronization Using Semaphores. EXAMPLE OPERATING SYSTEMS6. Introduction. 6. 4. Examples of Virtual Memory. Examples of Virtual I/O6. Examples of Process Management. SUMMARY7. 1 INTRODUCTION TO ASSEMBLY LANGUAGE7. What Is an Assembly Language? Why Use Assembly Language? Format of an Assembly Language Statement. Pseudoinstructions. MACROS7. 2. 1 Macro Definition, Call, and Expansion. Macros with Parameters. Advanced Features. Implementation of a Macro Facility in an Assembler. THE ASSEMBLY PROCESS7. Two- Pass Assemblers. Pass One. 7. 3. 3 Pass Two. The Symbol Table. LINKING AND LOADING7. Tasks Performed by the Linker. Structure of an Object Module. Binding Time and Dynamic Relocation. Dynamic Linking. 7. SUMMARY8. 1 ON- CHIP PARALELLISM8. Instruction- Level Parallelism. On- Chip Multithreading. Single- Chip Multiprocessors. COPROCESSORS8. 2. Network Processors. Media Processors. Cryptoprocessors. SHARED- MEMORYMULTIPROCESSORS8. Multiprocessors vs. Multicomputers. 8. Memory Semantics. UMA Symmetric Multiprocessor Architectures. NUMA Multiprocessors. COMA Multiprocessors. MESSAGE- PASSING MULTICOMPUTERS8. Interconnection Networks. MPPs–Massively Parallel Processors. Cluster Computing. Communication Software for Multicomputers. Scheduling. 8. 4. Application- Level Shared Memory. Performance. 8. 5 GRID COMPUTING8. SUMMARY9. 1 SUGGESTIONS FOR FURTHER READING9. Introduction and General Works. Computer Systems Organization. The Digital Logic Level. The Microarchitecture Level. The Instruction Set Architecture Level. The Operating System Machine Level. The Assembly Language Level. Parallel Computer Architectures. Binary and Floating- Point Numbers. Assembly Language Programming. ALPHABETICAL BIBLIOGRAPHYA. FINITE- PRECISION NUMBERSA. RADIX NUMBER SYSTEMSA. CONVERSION FROM ONE RADIX TO ANOTHERA. NEGATIVE BINARY NUMBERSA. BINARY ARITHMETICB. PRINCIPLES OF FLOATING POINTB. IEEE FLOATING- POINT STANDARD 7. C. 1 OVERVIEWC. 1. Assembly Language. C. 1. 2 A Small Assembly Language Program. C. 2 THE 8. 08. 8 PROCESSORC. The Processor Cycle. C. 2. 2 The General Registers. C. 2. 3 Pointer Registers. C. 3 MEMORY AND ADDRESSINGC. Memory Organization and Segments. C. 3. 2 Addressing. C. 4 THE 8. 08. 8 INSTRUCTION SETC. Move, Copy and Arithmetic. C. 4. 2 Logical, Bit and Shift Operations. Pearson - Modern Operating Systems, 4/EAbout This Product. Modern Operating Systems, Fourth Edition, is intended for introductory courses in Operating Systems in Computer Science, Computer Engineering, and Electrical Engineering programs. The widely anticipated revision of this worldwide best- seller incorporates the latest developments in operating systems (OS) technologies. The Fourth Edition includes up- to- date materials on relevant OS. Tanenbaum also provides information on current research based on his experience as an operating systems researcher. Modern Operating Systems, Third Editionwas the recipient of the 2. Mc. Guffey Longevity Award. The Mc. Guffey Longevity Award recognizes textbooks whose excellence has been demonstrated over time. http: //taaonline. Teaching and Learning Experience. This program will provide a better teaching and learning experience–for you and your students. It will help: Provide Practical Detail on the Big Picture Concepts: A clear and entertaining writing style outlines the concepts every OS designer needs to master. Keep Your Course Current: This edition includes information on the latest OS technologies and developments. Enhance Learning with Student and Instructor Resources: Students will gain hands- on experience using the simulation exercises and lab experiments. Features. Provide Practical Detail on the Big Picture Concepts. A clear and entertaining writing style outlines the concepts every OS designer needs to master. In- depth topic coverage includes processes, threads, memory management, file systems, I/O, deadlocks, interface design, multimedia, performance tradeoffs, and the newest trends in OS design. Multimedia file systems are covered–an important topic that most books miss. The chapter on Multimedia Operating Systems has been moved to the Web, primarily to make room for new material and keep the book from growing to a completely unmanageable size. A thorough treatment of computer security includes viruses, worms, malware and other digital pests. This chapter far exceeds anything written in any other book. It also discusses ways to combat them. Keep Your Course Current. Coverage of multiprocessors, multicomputers, virtual machines, and distributed systems reflects that the field is rapidly moving from an era of single- processor systems to multicore systems, multiprocessors, and distributed systems. Case studies of popular operating systems: UNIX, Linux, Windows 8, and Android NEW: Chapter 1. UNIX, Linux, and Android is a revision of the old Chapter 1. The focus is clearly on Linux now, with a great deal of new material about Android, which was not in the previous edition. NEW: Chapter 1. 1 in the third edition was on Windows Vista. A chapter on Windows 8, specifically Windows 8. It brings the treatment of Windows completely up to date. NEW and UPDATED: Chapters 2—6 have been updated, with older material removed and some new material added. Chapter 2: Added information on the futex synchronization primitive, and a section about how to avoid locking altogether with Read- Copy- Update. Chapter 3: More focus on modern hardware and less emphasis on segmentation and Multics. Chapter 4: CD- Roms are removed, as they are no longer very common, and replaced with more modern solutions (like flash drives). Also, we added RAID level 6 to the section on RAID. Chapter 5: Older devices like CRT and CD- ROMs have been removed, while new technology, like touch screens have been added. The sections on current research in these chapters have been rewritten from scratch. New problems and programming exercises have been added. NEW: Chapter 7 is completely new. It covers the important topics of virtualization and the cloud. NEW and UPDATED: Chapter 8 is an updated version of the previous material on multiprocessor systems. There is more emphasis on multicore systems now, which have become so important in the past few years. A long section on VMware has been added. NEW and UPDATED: Chapter 9 has been heavily revised and reorganized, with considerable new material on exploiting code bugs, malware, and defenses against them. UPDATED: Chapter 1. Chap. 1. 3 from the previous edition. A Research section in many chapters describes current research in the topic covered by the chapter. Enhance Learning with Student and Instructor Resources. Student Resources Include: Online Exercises provide hands- on experience with building as well as analyzing the performance of OS. In particular, these exercises have been designed to provide experience with analyzing the resource consumptions in Windows and Linux. Simulation Exercises are designed to provide experience with building some key components of an OS, including process scheduling, main memory allocation, paging algorithms and virtual memory, and file systems. Student Tools and Lab Experiments allow students to download the tools and run the experiments to gain deeper knowledge of the subject. Password- Protected Instructor Resources (Select the Resources Tab to View Downloadable Files): Power Point Lecture Slides. Figures in both . Solutions to Exercises. New To This Edition. Keep Your Course Current. Chapter 1 has been heavily modified and updated in many places but with the exception of a new section on mobile computers, no major sections have been added or deleted. Chapters 2—6 have been updated, with older material removed and some new material added. Chapter 2: Added information on the futex synchronization primitive, and a section about how to avoid locking altogether with Read- Copy- Update. Chapter 3: More focus on modern hardware and less emphasis on segmentation and Multics. Chapter 4: CD- Roms are removed, as they are no longer very common, and replaced with more modern solutions (like flash drives). Also, we added RAID level 6 to the section on RAID. Chapter 5: Older devices like CRT and CD- ROMs have been removed, while new technology, like touch screens have been added. The sections on current research in these chapters have been rewritten from scratch. New problems and programming exercises have been added. Chapter 7 is completely new. It covers the important topics of virtualization and the cloud. Chapter 8 is an updated version of the previous material on multiprocessor systems. There is more emphasis on multicore systems now, which have become so important in the past few years. A long section on VMware has been added. Chapter 9 has been heavily revised and reorganized, with considerable new material on exploiting code bugs, malware, and defenses against them. Chapter 1. 0, on UNIX, Linux, and Android is a revision of the old Chapter 1. The focus is clearly on Linux now, with a great deal of new material about Android, which was not in the previous edition. Chapter 1. 1 in the third edition was on Windows Vista. A chapter on Windows 8, specifically Windows 8. It brings the treatment of Windows completely up to date. Chapter 1. 2 is a revised version of Chap. Table of Contents. CHAPTER 1 "INTRODUCTION" 1. WHAT IS AN OPERATING SYSTEM? 3. The Operating System as an Extended Machine 4. The Operating System as a Resource Manager 5 1. HISTORY OF OPERATING SYSTEMS 6. The First Generation (1. Vacuum Tubes 7. The Second Generation (1. Transistors and Batch Systems 8. The Third Generation (1. ICs and Multiprogramming 9. The Fourth Generation (1. Present): Personal Computers 1. The Fifth Generation (1. Present): Mobile Computers 1. COMPUTER HARDWARE REVIEW 2. Processors 2. 11. Memory 2. 41. 3. Disks 2. 71. 3. I/O Devices 2. 81. Buses 3. 21. 3. Booting the Computer 3. THE OPERATING SYSTEM ZOO 3. Mainframe Operating Systems 3. Server Operating Systems 3. Multiprocessor Operating Systems 3. Personal Computer Operating Systems 3. Handheld Computer Operating Systems 3. Embedded Operating Systems. 3. Sensor- Node Operating Systems 3. Real- Time Operating Systems 3. Smart Card Operating Systems 3. OPERATING SYSTEM CONCEPTS 3. Processes 3. 91. Address Spaces 4. Files 4. 11. 5. Input/Output 4. Protection 4. 51. The Shell 4. 51. Ontogeny Recapitulates Phylogeny 4. SYSTEM CALLS 5. System Calls for Process Management 5. System Calls for File Management 5. System Calls for Directory Management 5. Miscellaneous System Calls 5. The Windows Win. 32 API 6. OPERATING SYSTEM STRUCTURE 6. Monolithic Systems 6. Layered Systems 6. Microkernels 6. Client- Server Model 6. Virtual Machines 6. Exokernels 7. 3 1. THE WORLD ACCORDING TO C 7. The C Language 7. Header Files 7. Large Programming Projects 7. The Model of Run Time 7. RESEARCH ON OPERATING SYSTEMS 7. OUTLINE OF THE REST OF THIS BOOK 7. METRIC UNITS 7. SUMMARY 8. 0CHAPTER 2 "PROCESSES AND THREADS" 2. PROCESSES 8. 52. The Process Model 8. Process Creation 8. Process Termination 9. Process Hierarchies 9. Process States 9. Implementation of Processes 9. Modeling Multiprogramming 9. THREADS 9. 72. 2. Thread Usage 9. The Classical Thread Model 1. POSIX Threads 1. Implementing Threads in User Space 1. Implementing Threads in the Kernel 1. Hybrid Implementations 1. Scheduler Activations 1. Pop- Up Threads 1. Making Single- Threaded Code Multithreaded 1. INTERPROCESS COMMUNICATION 1. Race Conditions 1. Critical Regions 1. Mutual Exclusion with Busy Waiting 1. Sleep and Wakeup 1. Semaphores 1. 30. Mutexes 1. 32. 2. Monitors 1. 37. Message Passing 1. Barriers 1. 46. Avoiding Locks: Read- Copy- Update 1. SCHEDULING 1. 49. Introduction to Scheduling 1. Scheduling in Batch Systems 1. Scheduling in Interactive Systems 1. Scheduling in Real- Time Systems 1. Policy Versus Mechanism 1. Thread Scheduling 1. CLASSICAL IPC PROBLEMS 1. The Dining Philosophers Problem 1. The Readers and Writers Problem 1. RESEARCH ON PROCESSES AND THREADS 1. SUMMARY 1. 73. CHAPTER 3 "MEMORY MANAGEMENT" 3. NO MEMORY ABSTRACTION 1. A MEMORY ABSTRACTION: ADDRESS SPACES 1. The Notion of an Address Space 1. Swapping 1. 87. Managing Free Memory 1. VIRTUAL MEMORY 1. Paging 1. 95. 3. Page Tables 1. 98. |
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October 2016
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